1. Field of the Invention
The present invention relates to a plasma display panel (PDP) driver.
2. Discussion of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma displays have been actively developed. Plasma displays have better luminance and light emission efficiency as compared to other types of flat panel devices, and they also have wider viewing angles. Therefore, the plasma displays have come into the spotlight as substitutes for the conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
The plasma display is a flat display that uses plasma generated by a gas discharge process to display characters or images, and tens to millions of pixels are provided thereon in a matrix format, depending on its size. Plasma displays are categorized into DC plasma displays and AC plasma displays, according to supplied driving voltage waveforms and discharge cell structures.
Since the DC plasma displays have electrodes exposed in the discharge space, they allow a current to flow in the discharge space while the voltage is supplied, and therefore they problematically require resistors for current restriction. On the other hand, since the AC plasma displays have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks during discharging. Accordingly, they have a longer lifespan than the DC plasma displays.
FIG. 1 shows a perspective view of an AC PDP. A scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed in parallel with the address electrodes 8, on the insulation layer 7 between the address electrodes 8, and phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1, 6 having a discharge space 11 between them are provided facing each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross the address electrode 8. The address electrode 8 and a discharge space 11 formed at a crossing point of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.
FIG. 2 shows a PDP electrode arrangement diagram for the AC PDP of FIG. 1. The PDP electrode arrangement has an m×n matrix configuration, with address electrodes A1 to Am in a column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in a row direction, alternately. The scan electrodes will be referred to as Y electrodes and the sustain electrodes as X electrodes hereinafter. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
Typically, the AC PDP driving method includes a reset period, an addressing period, and a sustain period according to temporally varied operations. FIG. 3 shows a conventional X and Y electrode waveform diagram. In the reset period wall charges caused by a previous sustain discharge are erased, and the cells are reset in order to stably perform a next address operation. In the address period, the cells that are turned on and the cells that are not turned on are selected on the panel, and wall charges are accumulated on the cells that are turned on (i.e., the addressed cells). In the sustain period, a discharge for actually displaying pictures on the addressed cells is performed by alternately applying a sustain discharge pulse Vs to the scan and sustain electrodes.
Conventionally, the same reset voltage is applied in all the reset periods. In this instance, a difference between the maximum voltage and the minimum voltage, that is, a voltage width, is substantially twice the discharge firing voltage. When initially driving a PDP set, the state of wall charges is varied depending on an operation when the PDP set is previously turned off or a time in which the turned-off state of the PDP set is maintained. Therefore, the cells may not be fully reset when a reset voltage which is the same as a reset voltage applied in a reset period in a normal operation is applied in an initial PDP set driving time.
It is possible to totally increase the reset voltage width in order to solve this problem. This, however, may apply an excessive reset voltage in the normal operation, increase a discharge amount of cells, increase background brightness, and thus degrade the contrast. Further, it increases a withstanding voltage of elements because of a high reset voltage, and increases a cost since an additional power supply for supplying a high voltage and a circuit are needed.